FFL and FFU instruction timing diagrams

The following timing diagram examples describe execution scenarios for the FFL (FIFO load) and FFU (FIFO unload) instructions.

Successful FFL execution followed by successful FFU execution

Successful FFL execution followed by successful FFU execution
Successful FFL execution followed by successful FFU execution
Scan cycle description
Scan Cycle
Description
1
Rung condition becomes TRUE when:
  • Execute input bit is TRUE.
  • Load (push) data to FIFO stack.
  • Done output bit is TRUE.
2,3,4
No change in rung condition.
5
Rung condition becomes FALSE when:
  • Execute bit is FALSE.
  • Done output bit is FALSE.
6, 7
No change in rung condition.
  • Execute bit is FALSE.
  • Done output bit is FALSE.
8
Rung goes TRUE when:
  • Execute input bit is TRUE.
  • Unload data from FIFO stack.
  • Done output bit is TRUE.
9
No change in rung condition.
  • Execute bit is FALSE.
  • Done output bit is FALSE.
10, 11
No change in rung condition.

Successful execution when the Empty bit is TRUE

Successful execution when the Empty bit is TRUE
Successful execution when the Empty bit is TRUE
Scan cycle description
Scan Cycle
Description
1
Rung condition becomes TRUE when:
  • Execute input bit is TRUE. Execution starts.
  • Position is zero. Empty bit is TRUE.
  • Done output bit is TRUE.
2,3,4
No change in rung condition.
5
Rung condition becomes FALSE when:
  • Execute bit is FALSE.
  • Empty bit is TRUE.
  • Done output bit is FALSE.
6, 7
No change in rung condition.
8
Rung goes TRUE when:
  • Execute input bit is TRUE. Execution starts.
  • Empty bit is TRUE.
  • Done output bit is TRUE.
9
Rung condition becomes FALSE when:
  • Execute bit is FALSE.
  • Empty bit is TRUE.
  • Done output bit is FALSE.
10, 11
No change in rung condition.

Successful execution when the Empty bit is TRUE

Successful execution when the Empty bit is TRUE
Successful execution when the Empty bit is TRUE
Scan cycle description
Scan Cycle
Description
1
Rung condition becomes TRUE when:
  • Execute input bit is TRUE. Execution starts.
  • Position is equal to Length, Full bit is TRUE.
  • Done output bit is TRUE. 
2,3,4
No change in rung condition.
5
Rung condition becomes FALSE when:
  • Execute bit is FALSE.
  • Full bit is TRUE.
  • Done output bit is FALSE.
6, 7
No change in rung condition.
8
Rung goes TRUE when:
  • Execute input bit is TRUE. Execution starts.
  • Full bit is TRUE.
  • Done output bit is TRUE.
9
Rung condition becomes FALSE when:
  • Execute bit is FALSE.
  • Full bit is TRUE.
  • Done output bit is FALSE.
10, 11
No change in rung condition.

Error encountered during FFL and FFU execution

Error encountered during FFL and FFU execution
Error encountered during FFL and FFU execution
Scan cycle description
Scan Cycle
Description
1
Rung condition becomes TRUE when:
  • Execute input bit is TRUE. Execution starts.
  • Error bit is TRUE.
2,3,4
No change in rung condition.
5
Rung condition becomes FALSE when:
  • Execute bit is FALSE.
  • Error and ErrorID bits are FALSE.
6, 7
No change in rung condition.
8
Rung goes TRUE when:
  • Execute input bit is TRUE. Execution starts.
  • Error bit is TRUE.
9
Rung condition becomes FALSE when:
  • Execute bit is FALSE.
  • Error and ErrorID bits are FALSE.
10, 11
No change in rung condition.
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