Socket instruction status bits
Bit Number | Name | Description |
|---|---|---|
0 | EN: Enable Bit | The EN bit is set when the instruction is enabled due to a False-to-True transition, but has not yet completed or erred. |
1 | EW: Enable Wait Queue Bit | The EW bit is set when the controller detects that a Socket instruction request has entered into queue. The controller resets the EW bit when the ST bit is set. |
2 | ST: Start Bit | The ST bit is set when the queued instruction is executing. The ST bit is reset when the DN or ER bit is set. |
3 | ER: Error Bit | Indicates that an error occurred while executing the instruction. The ER bit is reset the next time the run-condition-in goes from False to True. |
4 | DN: Done Bit | The DN bit is set when the Socket instruction completes successfully. The DN bit is reset the next time the run-condition-in goes from False to True. |
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